What's the difference between $stop and $finish in Verilog?

verilog
Steven picture Steven · Mar 7, 2010 · Viewed 60.3k times · Source

I'm using a GUI simulator, and they both seem to do the same thing.

Answer

user285321 picture user285321 · Mar 7, 2010

$finish exits the simulation and gives control back to the operating system.

$stop suspends the simulation and puts a simulator in an interactive mode.

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