Please explain this SystemVerilog syntax {>>byte{...}}

verilog system-verilog bit-shift
mitt2050 picture mitt2050 · Apr 12, 2014 · Viewed 9k times · Source

The answer for the following program is {6,7,8} but I don't understand why, please explain a bit:

module q ();
  typedef byte byteq[$];
  initial begin
    byte ans[$];

    ans = byteq'({>>byte{24'h060708}});
    $display("A:expect '{6,7,8} get %p", ans);
  end
endmodule

Answer

Ari picture Ari · Apr 12, 2014

The >> operator is not logical shift in this context, but it is called stream operator.

Stream operators determine the order in which blocks of data are streamed: >> causes blocks of data to be streamed in left-to-right order, while << causes blocks of data to be streamed in right-to-left order.

Consider the following lines for example:

$display ("%h",  {>>byte{24'h060708}} );
$display ("%h",  {<<byte{24'h060708}} );

In both, the number 24'h060708 should be first sliced into bytes (called slice_size). The first one prints the bytes from left to right, whereas the second one prints them from right to left. Therefor, the output is:

060708
080706

Now, in line ans = byteq'({>>byte{24'h060708}}); you are using bit-stream casting, which casts 24'h060708 number sliced in bytes represented from left to right into byteq, which is a queue of bytes.

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