How to define a parameterized multiplexer using SystemVerilog

verilog system-verilog
user2646276 picture user2646276 · Nov 9, 2013 · Viewed 20.4k times · Source

I am trying to create a module which switches x input data packets to a single output packet according to a one hot input.

If x was a fixed value of 4, I would just create a case statement,

case (onehot)
  4'b0001  : o_data = i_data[0];
  4'b0010  : o_data = i_data[1];
  4'b0100  : o_data = i_data[2];
  4'b1000  : o_data = i_data[3];
  default  : o_data = 'z;
endcase

But with variable x, how do I define all cases?

Thanks.

Answer

nguthrie picture nguthrie · Nov 9, 2013 
parameter X = 4;  

input [X-1:0] onehot;
input i_data [X];
output reg o_data;

always_comb 
begin
   o_data = 'z;
   for(int i = 0; i < X; i++) begin
      if (onehot == (1 << i))
         o_data = i_data[i];
   end
end

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