Assign a synthesizable initial value to a reg in Verilog

verilog
Frank Dejay picture Frank Dejay · Apr 4, 2012 · Viewed 109k times · Source

I'm an FPGA noob trying to learn Verilog. How can I "assign" a value to a reg in an always block, either as an initial value, or as a constant. I'm trying to do something like this in the code below. I get an error because the 8 bit constant doesn't count as input. I also don't want to trigger the always off of a clock. I just want to assign a register to a specific value. As I want it to be synthesisable I can't use an initial block. Thanks a lot. 

module top
(
    input wire clk,
    output wire [7:0] led   
 );


reg [7:0] data_reg ; 
always @*
begin
    data_reg = 8'b10101011;
end

assign led = data_reg;

endmodule

Answer

Nathan Farrington picture Nathan Farrington · Apr 4, 2012

You can combine the register declaration with initialization.

reg [7:0] data_reg = 8'b10101011;

Or you can use an initial block

reg [7:0] data_reg;
initial data_reg = 8'b10101011;

Related questions

How to declare and use 1D and 2D byte arrays in Verilog?

How to declare and use 1D and 2D byte arrays in Verilog? eg. how to do something like byte a_2D[3][3]; byte a_1D[3]; // using 1D for (int i=0; i< 3; i++) { a_1D[i] = (byte)i; } // using 2D for (…

Read More
Verilog: How to instantiate a module

If I have a Verilog module 'top' and a verilog module 'subcomponent' how do I instantiate subcomponent in top? top: module top( input clk, input rst_n, input enable, input [9:0] data_rx_1, input [9:0] data_rx_2, output [9:0] data_tx_2 ); subcomponent: module …

Read More
Using wire or reg with input or output in Verilog

When you declare something as input or output, how do you know if you have to also declare it as a reg or a wire?

Read More