Assign ASCII character to wire in Verilog

string ascii verilog system-verilog

Kevin Vermeer · Jan 27, 2012 · Viewed 28k times · Source

I understand that you can declare a string in a Verilog test bench as follows:

reg [8*14:1] string_value;  

initial 
    string_value = "Hello, World!";

I can then do things with this string, like use $display in a test bench to display it.

I haven't been successful in doing the same in a module when I flash it to my FPGA:

reg [8*14:1] string_value;  

always @(reset) 
begin
    string_value = "Hello, World!";
    // Do stuff with string value

Even assigning a single value does not work:

reg [8:1] char_value;  

always @(reset) 
begin
    char_value = "A";
    if (char_value == 8'h41)
        // Do stuff!

I want to shift the individual characters on an 8-bit bus to an LCD screen for display.

How can I work with strings in Verilog?

Answer

You can assign a string to a register type. Anyone who says otherwise is wrong. You might want to make your registers 0' based for it to work properly. I've done this in real FPGAs and it works.

Assign ASCII character to wire in Verilog

Answer

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