stm32f103 ADC sampling rate

stm32 adc
Radek23445 picture Radek23445 · Feb 10, 2017 · Viewed 13.9k times · Source

I set adc sample time cycles here :

ADC_RegularChannelConfig(ADC1, ADC_Channel_17, 1, ADC_SampleTime_71Cycles5);

How to calculate sampling rate of ADC from that in stm32f103 ?

Answer

Guillaume Michel picture Guillaume Michel · Feb 11, 2017

You haven't provided enough information to give an exact number. But here what you should know. You have selected the sampling time to be 71.5 ADC clock cycles. The ADC clock is generated by PCLK2 via the ADC prescaler. The ADC prescaler is in the RCC_CFGR register. For example, if PCLK2 is 72MHz and ADC prescaler is 6, ADC clock is 12MHz. And the sampling time is 71.5 cycles which translates to 71.5/12 ~ 6us

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