Top "Cpu-architecture" questions

The hardware microarchitecture (x86, x86_64, ARM, ...) of a CPU or microcontroller.

Determining page numbers and offsets for given addresses

Consider a computer system with a 32-bit logical address and 4KB page size. The system supports up to 512MB of …

memory-management operating-system offset cpu-architecture virtual-memory
How to use Fused Multiply-Add (FMA) instructions with SSE/AVX

I have learned that some Intel/AMD CPUs can do simultanous multiply and add with SSE/AVX: FLOPS per cycle …

c sse cpu-architecture avx fma
What is a CPU thread and how is it related to logical threads in code?

I have been seeing in the literature for some of the newer CPU's such as the Intel Xeon "Nehalem-EX" as …

multithreading cpu-architecture hyperthreading
Why is the page size of Linux (x86) 4 KB, how is that calculated?

The default memory page size of the Linux kernel on x86 architecture was 4 KB, I wonder how was that calculated, …

linux x86 kernel cpu-architecture
Why is x86 ugly? Why is it considered inferior when compared to others?

Recently I've been reading some SO archives and encountered statements against the x86 architecture. Why do we need different CPU …

assembly x86 mips x86-64 cpu-architecture
Where is the L1 memory cache of Intel x86 processors documented?

I am trying to profile and optimize algorithms and I would like to understand the specific impact of the caches …

performance intel cpu-architecture cpu-cache
What's the purpose of the rotate instructions (ROL, RCL on x86)?

I always wondered what's the purpose of the rotate instructions some CPUs have (ROL, RCL on x86, for example). What …

assembly x86 cpu-architecture machine-instruction
Why is x86 little endian?

A real question that I've been asking myself lately is what design choices brought about x86 being a little endian …

x86 intel endianness cpu-architecture microprocessors
why are separate icache and dcache needed

Can someone please explain what do we gain by having a separate instruction cache and data cache. Any pointers to …

caching x86 cpu-architecture cpu-cache
atomic operation cost

What is the cost of the atomic operation (any of compare-and-swap or atomic add/decrement)? How much cycles does it …

performance atomic cpu-architecture lock-free