How to use const in verilog

Question

Instead of using

module ... ( .. )  ;

     #15 
endmodule

I want use

module ... ( ... ) ;
 // GateDelay is a const, like in c language const int GateDelay = 15 ;
 # GateDelay     

endmodule

Or same thing

module ... ( ... ) ;
 // assume Wordsize is defined at " define Wordsize 15 "
 reg [ Wordsize -1 : 0 ] mem ;

endmodule

Can I do that wish in verilog ?

Answer 1

You've a few options :

• Macros with `defines
• parameters
• localparams

Here's a small example with them all.

`define CONSTANT_MACRO 1          /* important: no ';' here */
module mymodule
    #( parameter WIDTH = 5 )
    ( 
      input wire [WIDTH-1:0] in_a,
      output wire [WIDTH-1:0] out_a
    );

    localparam CONSTANT_LOCAL = 2;

    assign out_a = in_a + `CONSTANT_MACRO - CONSTANT_LOCAL;

endmodule