VHDL Case/When: multiple cases, single clause

case vhdl

Jay Wick · Sep 14, 2010 · Viewed 32k times · Source

Inside a process I have something like this:

CASE res IS
  WHEN "00" => Y <= A;
  WHEN "01" => Y <= A;
  WHEN "10" => Y <= B;
  WHEN "11" => Y <= C;
  WHEN OTHERS => Y <= 'X';
END CASE;

Note that case "00" and "01" get the same value. Is there a correct syntax for something like

WHEN "00", "01" => ?

Extra note: There's far more to this than Y being changed, I just used that for simplicity. So the case/when is necessary.

Answer

You can separate multiple choices with the "pipe" or bar symbol. The proper syntax for your example is:

CASE res IS
  WHEN "00" | "01" => Y <= A;
  WHEN "10" => Y <= B;
  WHEN "11" => Y <= C;
  WHEN OTHERS => Y <= 'X';
END CASE;