I want to know the difference between FIQ and IRQ interrupt system in any microprocessor, e.g: ARM926EJ.
ARM calls FIQ
the fast interrupt, with the implication that IRQ
is normal priority. In any real system, there will be many more sources of interrupts than just two devices and there will therefore be some external hardware interrupt controller which allows masking, prioritization etc. of these multiple sources and which drives the interrupt request lines to the processor.
To some extent, this makes the distinction between the two interrupt modes redundant and many systems do not use nFIQ
at all, or use it in a way analogous to the non-maskable (NMI
) interrupt found on other processors (although FIQ
is software maskable on most ARM processors).
So why does ARM call FIQ "fast"?
r8-r14
. R14 is the link register which holds the return address(+4) from the FIQ. But if your FIQ handler is able to be written such that it only uses r8-r13
, it can take advantage of these banked registers in two ways:
r8
may be used as a pointer to a hardware device and the handler can rely on the same value being in r8
the next time it is called.0x1C
) means that if the FIQ handler code is placed directly at the end of the vector table, no branch is required - the code can execute directly from 0x1C
. This saves a few cycles on entry to the ISR.So why do many systems not use FIQ?
r8-r13
. Code produced by a C compiler compliant with ARM's ATPCS
procedure call standard will instead use registers r0-r3
for scratch values and will not produce the correct cpsr
restoring return code at the end of the function.