I am reasonably new to the ARM architectures and I am trying to wrap my head around the wake up mechanism.
So first of all I am finding it difficult to find good info on this. ARM's documentation seems to be very terse on the topic.
What I'd like to understand is when the Cortex (particularly the M0 as that's what I am working with) will wake up.
For reference, I have also consulted the following:
The docs on the WFE instructions are:
3.7.11. WFE
Wait For Event.
Syntax
WFE
Operation
If the event register is 0, WFE suspends execution until
one of the following events occurs:
an exception, unless masked by the exception mask registers or the current
priority level
an exception enters the Pending state, if SEVONPEND in the
System Control Register is set
a Debug Entry request, if debug is enabled
an event signaled by a peripheral or another processor in a
multiprocessor system using the SEV instruction.
If the event register is 1, WFE clears it to 0 and completes immediately.
For more information see Power management.
Note
WFE is intended for power saving only. When writing software assume
that WFE might behave as NOP.
Restrictions
There are no restrictions.
Condition flags
This instruction does not change the flags.
Examples
WFE ; Wait for event
The WFI:
3.7.12. WFI
Wait for Interrupt.
Syntax
WFI
Operation
WFI suspends execution until one of the following events occurs:
an exception
an interrupt becomes pending, which would preempt if PRIMASK was clear
a Debug Entry request, regardless of whether debug is enabled.
Note
WFI is intended for power saving only. When writing software assume
that WFI might behave as a NOP operation.
Restrictions
There are no restrictions.
Condition flags
This instruction does not change the flags.
Examples
WFI ; Wait for interrupt
So, some questions:
1) Firstly, can someone please clarify the difference between:
a) System Handler Priority Registers
b) Interrupt Priority Registers. Is it just that b) are for interrupts that aren't system related such as pendSv?
Now for some scenarios. Really I would like to understand how the scenarios governed by the: NVIC IRQ enable NVIC pending PRIMASK
affect the entry and exit of WFE and WFI.
So the various combinations of these bits yields 8 different scenarios {NVIC_IRQ enable, NVIC pending, PRIMASK}.
I have already added my vague understanding so far. Please help me with this table.
I am excluding the priorities here as I'm not too concerned about the exception handling order just yet.
Excluding SEV and the event signals, does WFE behave the same as WFI if SEVONPEND is 0?
The primary mechanism for wake that you'll see on a Cortex-M is an interrupt, hence WFI (wait for interrupt). On all of the implementations that I've seen that results in clock-gating the core, although deeper sleep/higher latency modes are sometimes available if the design supports it.
WFE is more relevant in multi-processor designs.
With regard to the questions - 1. Interrupts and System Handlers are very similar in the Cortex-M, differing primarily by how they are triggered. The architecture distinguishes between them, but in practice they are the same.
Are for your bit tables, they don't really make sense. Each Cortex-M implementation has it's own interpretation of what happens during WFI. It can vary from basic clock gating to deep-sleep modes. Consult your microprocessor documentation for the real story.
PRIMASK doesn't affect wake from sleep behavior.