Is x86 RISC or CISC?

wowpatrick picture wowpatrick · Oct 25, 2012 · Viewed 56.8k times · Source

According to Wikipedia, x86 is a CISC design, but I also have heard/read that it is RISC. What is correct? I'd to also like to know why it is CISC or RISC. What determines if a design is RISC or CISC? Is it just the number of machine language instruction a microprocessors has or are there any other characteristics that determine the architecture?

Answer

mikeswright49 picture mikeswright49 · Oct 25, 2012

x86 is a CISC architecture. The number of instructions is a big factor as all cisc architectures with all more instructions. Furthermore as instructions are complex in cisc they can take >1 cycle to complete, where as in RISC they should be single cycle. The main differences are found here:

+------------------------------+------------------------------+
| CISC                         | RISC                         |
+------------------------------+------------------------------+
| Emphasis on hardware         | Emphasis on software         |
| .                            |                              |
| Includes multi-clock         | Single-clock,                |
| complex instructions         | reduced instruction only     |
| .                            |                              |
| Memory-to-memory:            | Register to register:        |
| "LOAD" and "STORE"           | "LOAD" and "STORE"           |
| incorporated in instruction  | are independent instructions |
| .                            |                              |
| Small code sizes,            | Low cycles per second,       |
| high cycles per second       | large code sizes             |
| .                            |                              |
| Transistors used for storing | Spends more transistors      |
| complex instructions         | on memory registers          |
+------------------------------+------------------------------+

For further research consult here: http://www-cs-faculty.stanford.edu/~eroberts/courses/soco/projects/risc/risccisc/