I have a C shell script that does something like this:
#!/bin/csh
gcc example.c -o ex
gcc combine.c -o combine
ex file1 r1 <-- 1
ex file2 r2 <-- 2
ex file3 r3 <-- 3
#... many more like the above
combine r1 r2 r3 final
\rm r1 r2 r3
Is there some way I can make lines 1
, 2
and 3
run in parallel instead of one after the another?
Convert this into a Makefile with proper dependencies. Then you can use make -j
to have Make run everything possible in parallel.
Note that all the indents in a Makefile must be TABs. TAB shows Make where the commands to run are.
Also note that this Makefile is now using GNU Make extensions (the wildcard and subst functions).
It might look like this:
export PATH := .:${PATH}
FILES=$(wildcard file*)
RFILES=$(subst file,r,${FILES})
final: combine ${RFILES}
combine ${RFILES} final
rm ${RFILES}
ex: example.c
combine: combine.c
r%: file% ex
ex $< $@