what is the difference between -> and => in system verilog assertions?

system-verilog assertions system-verilog-assertions
vivek M picture vivek M · Oct 18, 2015 · Viewed 9.6k times · Source

I wanted to know when to use -> and => in SVA ? Are there any differences between 

sequence A;
 req |-> ##1 gnt;
endsequence

and 

sequence B;
 req |=> ##1 gnt;
endsequence

Please let me know.. Thank you.

Answer

dave_59 picture dave_59 · Oct 19, 2015

The difference is when the antecedent (the expression on the left) succeeds, does the consequent (the expression on the right) start on the same clock cycle |-> (overlapping) or the next clock cycle |=> (non-overlapping).

A handy way to remember this is there is only one bar in -, so that is overlapping. And there is are two bars in =, so that is non-overlapping.

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