Ones count system-verilog

system-verilog
Void Star picture Void Star · Nov 29, 2014 · Viewed 17.5k times · Source

I have a wire vector with 64 bits;

wire [63:0] sout;

I want to compute the sum of these bits or, equivalently, count the number of ones.

What is the best way to do this? (it should be synthesizable)

Answer

Greg picture Greg · Dec 1, 2014

I prefer using for-loops as they are easier to scale and require less typing (and thereby less prone to typos).

SystemVerilog (IEEE Std 1800):

logic [$clog2($bits(sout)+1)-1:0] count_ones;

always_comb begin
  count_ones = '0;  
  foreach(sout[idx]) begin
    count_ones += sout[idx];
  end
end

Verilog (IEEE Std 1364-2005):

parameter WIDTH = 64;
// NOTE: $clog2 was added in 1364-2005, not supported in 1364-1995 or 1364-2001
reg [$clog2(WIDTH+1)-1:0] count_ones; 
integer idx;

always @* begin
  count_ones = {WIDTH{1'b0}};  
  for( idx = 0; idx<WIDTH; idx = idx + 1) begin
    count_ones = count_ones + sout[idx];
  end
end

Related questions

Verilog: How to instantiate a module

If I have a Verilog module 'top' and a verilog module 'subcomponent' how do I instantiate subcomponent in top? top: module top( input clk, input rst_n, input enable, input [9:0] data_rx_1, input [9:0] data_rx_2, output [9:0] data_tx_2 ); subcomponent: module …

Read More
Indexing vectors and arrays with +:

I am seeing a code in SystemVerilog which has something like this: if(address[2*pointer+:2]) do_something; How should I understand the +: when indexing this vector? I found that it is called bit slicing, but I can't find an explanation …

Read More
Difference of SystemVerilog data types (reg, logic, bit)

There are different data types in systemverilog that can be used like the following: reg [31:0] data; logic [31:0] data; bit [31:0] data; How does the three of them differ?

Read More