Difference among always_ff, always_comb, always_latch and always

system-verilog
user2138826 picture user2138826 · Apr 16, 2014 · Viewed 65.9k times · Source

I am totally confused among these 4 terms: always_ff, always_comb, always_latch and always. How and for what purpose can these be used?

Answer

Morgan picture Morgan · Apr 16, 2014

always is the main type of process from Verilog, the other is an initial which is ran once at the start of a simulation.

always_ff @(posedge clk) :
Represents a flip-flop (ff), the process is triggered (executed) on every positive edge of the clock. This replaces always @(posedge clk). This is the only type where non-blocking (<=) assignments should be used, as this mimics the way a flip-flop transfers data.

always_ff @(posedge clk) begin
  a <= b;
end

always_latch : is for representing latches.

Usage would be :

always_latch begin
  if (enable) begin
     a_latch = something;
  end
  //No else clause so a_latch's value
  //is not always defined, so it holds its value
end

This replaces :

always @* begin
  if (enable) begin
     a_latch = something;
  end
  //No else clause so a_latch's value
  //is not always defined, so it holds its value
end

always_comb:
Is for combinatorial logic, it is replacement for always @* when you do not want a latch. Now we can now differentiate our design intent between when we want and do not want latches.

The SystemVerilog names always_ff, always_latch and always_comb have stricter criteria for when they are triggered, this means the chance for RTL to Gate level (post synthesis) mismatch is reduced. It does mean the are not 100% equivalent to there always @ counter part and may change some simulation behaviour.

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