How is a PCI / PCIe BAR size determined?
I know that the base address register (BAR) in PCI configuration space defines the start location of a PCI address, but how does the size of this region get established?
Surely this is a property of the hardware since only it knows how far into its address space it can deal. However, I cannot seem to see a BAR size field in the PCI configuration structure.
Answer
First of all, the BAR size must be a power of two (e.g., 1 KiB, 2 MiB), and each area must be aligned in memory such that the lower log2(size) bits of the base address are always zero. For example, assume that an endpoint has a 4 KiB memory area, which gives an address range of 0-0xfff. The host may remap the start of this area to f.x. 0x1000 or 0xabcd000 by writing to the BAR register, but not to 0x1080 or 0xabcd100.
When the BAR register is written, the endpoint will ignore LSBs and always return zeros on read. Thus writing 0xffffffff to the register and then reading back the value indicates the size of the area. For the 4 KiB example this returns 0xfffff00X (the lower four bits are reserved, see specification). To determine the size:
- Clear the lower four bits to zeros (
0xfffff000) - Invert all 32 bits (
0xfff) - Add one to the result (
0x1000 = 4096 bytes)
This works for 64-bit areas as well. The value of the next base address register forms the MSBs of the base address. This is described in section 6.2.5.1 of the PCI 3.0 specification.