Can a PCIe endpoint access Root Complex BARs?

pci-e
user2504336 picture user2504336 · Jun 20, 2013 · Viewed 9.7k times · Source

I am working on an embedded PCIe system where two SoCs are connected together, the Host is a Root Complex, the Slave is an Endpoint. The Host will run Linux.

Typically the Host SoC provides memory windows, where the Endpoint BARs are mapped. This allows a card driver on the Host to read/write to IO or memory on the Slave. Often, the Slave will include a DMAC built into the PCIe IP, that works with a PCIe address and a local address. The Host will setup this DMAC by writing to the memory windows.

In my case, the Endpoint doesn't have a DMAC built in to the PCIe IP, but is does have a system DMAC. So, two questions...

  1. Can an Endpoint access the Root Complex's memory via BARs?
  2. Are there any performance implications of using a system DMAC instead of built in PCIe DMAC? (in other words, how do accesses via BARs appear on the PCIe bus, do you get one TLP for each access?)

Any help appreciated!

Answer

Nadav picture Nadav · Jun 20, 2013

  1. The BARs reside within the legacy confiuration space. As of such, that register can only be reached with a CfgRd or CfgWr. These TLPs (Transaction Layer Packets) can only be originated from an RC. So how would the EP know what are the valid memory addresses of the RC ? tough question, the PCI-Express specification have no answer for that. In reality there are regions that are more likely to be allocated than others, so you can make an educated guess.

  2. Accessing a BAR requires at least 2 TLPs: the request (CfgWr or CfgRd) and the appropriate completion (Cpl or CplD, respectively).

I hope that helps,

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