timing diagram of Memory Read Cycle in 8085 Microprocessor
From the topic of Memory Read Machine Cycle, I got an example of timing diagram for MVI instruction.
Again in another topic Memory Interfacing, the book shows timing diagram of Memory Read Cycle. Here 8085 provides two signals – IO/M(bar) and RD(bar) to indicate that it is a memory read operation. The IO/M(bar) and RD(bar) can be combined to generate the MEMR(bar) (Memory Read) control signal that can be used to enable the output buffer by connecting to the memory signal RD(bar). And the memory places the data byte from the addressed register during T2, & that is read by the microprocessor before the end of T2. Why in this diagram there is arrow from IO/M to RD and from RD to MEMR?
Both the figure says Memory Read Cycle but there are some differences in the two timing diagrams in M2. Please can anyone explain when to use the first one and when to use the second timing diagram.
Answer
The arrow specifies that this line is the one that can be affected due to change in another line.
There are two types broadly: 1. Single line single effect (as in the opcode fetch cycle) 2. Multiple line single effect (as in the memory addressing)
As you can see in the opcode fetch cycle, whenever the Rd\ line changes, there is a change in the AD7 -AD0 lines. So this is a single line with single effect
And, in case of memory addressing, a change in Rd\ brings a change in MEMR\ which brings a change in AD7 - AD0 so it is a multiple line with single effect. I'm not sure why the arrow goes from Io/M\ line.
You might wanna look at the timing diagram of 8085 as a whole on the internet.