Controlling verbosity of make

Question

I'm using a makefile to compile a program made of many .c files, and any time make is invoked it only compiles those files modified after the last run (nothing special until here).

To avoid cluttering my screen, I prepend @ at the beginning of each $(CC) call, and before it I print a customized echo message. For example:

%.o: %.c $(h1) $(h3) %.h
    @echo -e "\tCompiling <" $< 
    @$(CC) $(CFLAGS) -c $< -o $(libDir)$@$(MATHOPTS)

My question is: how can I control the verbosity of make in a more "dynamic way", in order to be able to:

1. Normal behaviour: only a customized message is printed for every makefile rule executed.
2. Verbose behaviour: print the command actually executed by every makefile rule (as if the @ wasn't used at all).

Answer 1

I'd do it the way automake does:

V = 0
ACTUAL_CC := $(CC)
CC_0 = @echo "Compiling $<..."; $(ACTUAL_CC)
CC_1 = $(ACTUAL_CC)
CC = $(CC_$(V))

%.o: %.c $(h1) $(h3) %.h
        $(CC) $(CFLAGS) -c $< -o $(libDir)$@$(MATHOPTS)

If you need to execute other commands in your rules, I like the following snippet. Write $(AT) instead of @ and it will be silent when V=0 but printed when V=1.

AT_0 := @
AT_1 := 
AT = $(AT_$(V))