Heredoc in a Makefile?

makefile gitignore heredoc
nalply picture nalply · May 3, 2011 · Viewed 19.1k times · Source

Is this possible at all and how?

Update: I need this because I create a file both from dynamic and static data.

Use case: I have a test directory. Each C file produces a test executable. With

SRCS = $(wildcard [a-z]*.c)

I can add new tests as needed and make will find the new tests, compile, run and valgrind them. I also use git. I would like .gitignoreto include the executables.

So there. How to create .gitignore and include static data, i.e. the files I want to be ignored (*.o and depend) and also the executables dynamically?

Answer

Ash Berlin-Taylor picture Ash Berlin-Taylor · Sep 11, 2011

Another GNU Make solution.

You can do it using the define and export commands as follows:

define GITIGNOREDS
*.o
depend
endef

SRCS = $(wildcard [a-z]*.c)
EXES = $(SRCS:.c=)


export GITIGNOREDS
.gitignore: $(SRCS)
    echo $(EXES) | sed 's/ /\n/g' > $@
    echo "$$GITIGNOREDS" >> $@

You have to be careful of make expansions (i.e. $(x)) inside the define block though.

Related questions

gcc makefile error: "No rule to make target ..."

I'm trying to use GCC (linux) with a makefile to compile my project. I get the following error which is can't seem to decipher in this context: "No rule to make target 'vertex.cpp', needed by 'vertex.o'. Stop." This …

Read More
How to run a makefile in Windows?

I have some demos that I downloaded and they come with a Makefile.win and a Makefile.sgi. How can I run these in Windows to compile the demos?

Read More
Passing additional variables from command line to make

Can I pass variables to a GNU Makefile as command line arguments? In other words, I want to pass some arguments which will eventually become variables in the Makefile.

Read More