Checking if variables are defined in a makefile

Question

I have a GNU Makefile (version 3.81) that looks like the following:

.PHONY: SPOneDot

SPOneDot:
    ifndef X
    X=0.05
    $$(info X undefined, changed to $X)
    endif
    ifndef Y
    Y=0.05
    $$(info Y undefined, changed to $Y)
    endif
    python ./Submit3DSP.py -f OneDot.qdt -x $(X) -y $(Y)

I execute with the following command line: make X=0.1 Y=0.1 SPOneDot but I get the following result:

ifndef X
make: ifndef: Command not found
make: *** [SPOneDot] Error 127

I've looked in the makefile documentation and seen others use it. Any help is appreciated, it's likely something foolish.

Answer 1

Most likely your make directives must not be tab indented but start in the first column. I also suspect you want .if(...) or similar, not plain ifdef. It's hard to tell without knowing what make implementation you use.

In GNU make, conditional parts are used e.g. like this

ifeq ($(CC),gcc)
        $(CC) -o foo $(objects) $(libs_for_gcc)
else
        $(CC) -o foo $(objects) $(normal_libs)
endif

The GNU make manual has all the details.

If you really mean to test an environment variable (as opposed to a make variable), then simply do so in the commands:

SPOneDot:
    if test -z "$$X"; then X=0.05; echo "X undefined, changed to $$X"; fi; \
    if test -z "$$Y"; then Y=0.05; echo "Y undefined, changed to $$Y"; fi; \
    python ./Submit3DSP.py -f OneDot.qdt -x $$X -y $$Y

Note that $$ is passed to the shell as a single $ and everything must be a single command for the shell, hence the semicolons and backslash/newlines.