Which Cortex-M3 interrupts can I use for general purpose work?

embedded interrupt cortex-m3
Captain NedD picture Captain NedD · May 2, 2010 · Viewed 9.9k times · Source

I'd have some code that needs to be run as the result of a particular interrupt going off.

I don't want to execute it in the context of the interrupt itself but I also don't want it to execute in thread mode.

I would like to run it at a priority that's lower than the high level interrupt that precipitated its running but also a priority that higher than thread level (and some other interrupts as well).

I think I need to use one of the other interrupt handlers.

Which ones are the best to use and what the best way to invoke them?

At the moment I'm planning on just using the interrupt handlers for some peripherals that I'm not using and invoking them by setting bits directly through the NVIC but I was hoping there's a better, more official way.

Thanks,

Answer

Miro Samek picture Miro Samek · May 3, 2010

ARM Cortex supports a very special kind of exception called PendSV. It seems that you could use this exception exactly to do your work. Virtually all preemptive RTOSes for ARM Cortex use PendSV to implement the context switch.

To make it work, you need to prioritize PendSV low (write 0xFF to the PRI_14 register in the NVIC). You should also prioritize all IRQs above the PendSV (write lower numbers in the respective priority registers in the NVIC). When you are ready to process the whole message, trigger the PendSV from the high-priority ISR:

*((uint32_t volatile *)0xE000ED04) = 0x10000000; // trigger PendSV

The ARM Cortex CPU will then finish your ISR and all other ISRs that possibly were preempted by it, and eventually it will tail-chain to the PendSV exception. This is where your code for parsing the message should be.

Please note that PendSV could be preempted by other ISRs. This is all fine, but you need to obviously remember to protect all shared resources by a critical section of code (briefly disabling and enabling interrupts). In ARM Cortex, you disable interrupts by executing __asm("cpsid i") and you enable interrupts by __asm("cpsie i"). (Most C compilers provide built-in intrinsic functions or macros for this purpose.)

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