Direct-Mapped Cache Hit & Miss
4-bit address
tag 1-bit
index 2-bit
offset 1-bit
2 bytes per block
4 sets (1 block per set)
I am trying to determine if the following addresses are hits or misses. I am presenting the information I have acquired thus far. (all credit will be given to stack overflow)
Addresses
14
set 3
v = 0
tag = 1
offset = 0
9
set 0
v = 0
tag = 1
offset = 1
2
set 1
v = 0
tag = 0
offset = 0
6
set 3
v = 1
tag = 0
offset = 0
3
set 1
v = 1
tag = 0
offset = 1
Answer
As it's a direct mapped cache, and it has 4 sets, this means that it has a capacity for 4 blocks.
1) Address 14 which in binary is: 1110
Assuming that in the beginning the cache is empty, we got a miss and we store this word on the cache. Tag 1, at set #3.
2) Address 9 which in binary is: 1001
Tag 1 , Set #0, we got a miss. Therefore we store it on set 0.
3) Address 2 in binary; 0010
this block goes on set 1 and it's empty. We got a miss and store it. With the tag 0
4) Address 6 in binary: 0110 As we already have stored a block in set 3, we compare it. As their tags are different Tag 0 != Tag 1 we evict the previous one and we store the new one. Miss
5)Address 3 in binary: 0011 this block goes in set 1 and as we already had a block in set 1 we compare it. As their tags are equal 0 = 0, we got a HIT.