Multiline bash commands in makefile

Question

I have a very comfortable way to compile my project via a few lines of bash commands. But now I need to compile it via makefile. Considering, that every command is run in its own shell, my question is what is the best way to run multi-line bash command, depended on each other, in makefile? For example, like this:

for i in `find`
do
    all="$all $i"
done
gcc $all

Also, can someone explain why even single-line command bash -c 'a=3; echo $a > file' works correct in terminal, but create empty file in makefile case?

Answer 1

You can use backslash for line continuation. However note that the shell receives the whole command concatenated into a single line, so you also need to terminate some of the lines with a semicolon:

foo:
    for i in `find`;     \
    do                   \
        all="$$all $$i"; \
    done;                \
    gcc $$all

But if you just want to take the whole list returned by the find invocation and pass it to gcc, you actually don't necessarily need a multiline command:

foo:
    gcc `find`

Or, using a more shell-conventional $(command) approach (notice the $ escaping though):

foo:
    gcc $$(find)