ARM assembly code and SVC numbering

daehee picture daehee · Jun 11, 2014 · Viewed 10.9k times · Source

In ARM assembly codes I can see something like these... (especially in shellcodes)

svc 0x0090003f
svc 0x001ff3bf
swi 0x0900ff0b

I know that 'svc(or swi)' is the 'supervisor call' like 'int 0x80' or 'SYSENTER' from Intel. but, how can I interpret the 'svc' numbers?? where can I get the listing of it's information?? What about thumb 'svc' instruction??

The arm instruction manual doesn't seem to be explaining these...

Can someone help me? Thank you in advance.

Answer

Ciro Santilli picture Ciro Santilli · Jul 16, 2019

The SVC value gets stored in the 16-bits low bits of the ESR register

The ARMv8 Architecture Reference D12.2.36 "ESR_EL1, Exception Syndrome Register (EL1)" says that if the EC bits are 0b010101 then the ISS field is documented at "ISS encoding for an exception from HVC or SVC instruction execution".

That section then says that the lower 16 bits are imm16, which if you look at the SVC definition is the name given to the 16-bit argument.

Finally, the SVC calls you shows on your question are not valid in ARMv8 GNU GAS, because they are larger than 16-bits. For example:

SVC 0xABCDE

correctly fails to assemble with:

Error: immediate value out of range 0 to 65535 at operand 1 -- `svc 0xABCDE

Runnable example

Here is a minimalistic aarch64 baremetal runnable example that does an SVC and prints out all registers during the handler, including ESR https://github.com/cirosantilli/linux-kernel-module-cheat/tree/b1bfd46efebabcba4f1ab1cbddf99611550e2dc2#arm-svc-instruction